The present invention relates to a semiconductor device, to a method of manufacturing the same, and to an electro-optical device.
As an electro-optical device, such as a liquid crystal display device, an organic electroluminescent (EL) device, a plasma display device, and the like, an active-matrix-type electro-optical device in which thin film transistors (TFTs) serving as thin film semiconductor devices are provided in a plurality of pixels arranged in a matrix in order to drive the plurality of pixels has been widely used. In the TFT, it is common to form amorphous silicon or polycrystalline silicon as a channel region. Particularly, since electrons or holes in a polycrystalline silicon TFT manufactured by only a low-temperature process have high mobility due to a high electric field, the polycrystalline silicon TFT has been employed for electro-optical devices, such as liquid crystal display devices, organic EL devices, and the like.
As the TFT, a TFT having a lightly doped drain (LDD) structure and a TFT having a gate-drain overlapped LDD (GOLD) structure have been well known. The TFT having the LDD structure has a structure in which a lightly doped impurity region is formed in a polycrystalline silicon layer corresponding to an outer region outside a region immediately under a gate electrode and a heavily doped impurity region, which become a source region and a drain region, is formed in the outer region, thereby suppressing an off current value. On the other hand, the TFT having the GOLD structure has a structure in which the lightly doped impurity region having the LDD structure is formed up to a region immediately under an end portion of a gate electrode in such a manner that the lightly doped impurity region overlaps the end portion, thereby suppressing a hot carrier phenomenon.
As one example of methods of forming the TFT having the LDD and GOLD structures, disclosed is a method in which the LDD structure is formed by forming a resist pattern having a region whose edge portion has a film thickness smaller than that of its center portion using a photomask or the like having a diffraction grating pattern, etching a conductive film in such a manner that a gate electrode having a region whose edge portion has a film thickness smaller than that of its center portion is formed, and implanting impurities into a semiconductor layer using a mask electrode as a mask (for example, see Japanese Unexamined Patent Application Publication No. 2002-151523 which is an example of the related art).
In the method of forming the TFT having the LDD and GOLD structures disclosed in the related art, both end portions of the gate electrode are dry etched using the resist pattern as a mask pattern such that the residual film thickness becomes 5% to 30% of the initial film thickness, and then, a lightly doped impurity region is formed in the semiconductor layer using the gate electrode as the mask.
However, in the method of forming the TFT having the LDD and GOLD structures, the selectivity ratio of dry etching should be considered in order to control the film thickness of the gate electrode to be a desired thickness. This may cause complexity of machining of the gate electrode. In addition, when the selectivity ratio is considered in order to control the film thickness of the gate electrode in dry etching as mentioned above, a problem occurs in that the selection of the material of the gate electrode, the etchant and the like to obtain a desired selectivity ratio is limited.